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1DDR2 Device Operations & Timing DiagramDDR2 SDRAM Device Operation&Timing Diagram

10DDR2 Device Operations & Timing DiagramEMR(3)No function is defined in extended mode register(3). The default value of the extended mode registe

11DDR2 Device Operations & Timing Diagram1.2.2.3 Off-Chip Driver (OCD) Impedance AdjustmentDDR2 SDRAM supports driver calibration feature and the

12DDR2 Device Operations & Timing DiagramExtended Mode Register for OCD impedance adjustmentOCD impedance adjustment can be done using the follow

13DDR2 Device Operations & Timing DiagramFor proper operation of adjust mode, WL = RL - 1 = AL + CL - 1 clocks and tDS/tDH should be met as the fo

14DDR2 Device Operations & Timing Diagram1.2.2.4 ODT (On Die Termination)On Die Termination (ODT) is a feature that allows a DRAM to turn on/off t

15DDR2 Device Operations & Timing DiagramODT timing for active/standby mode ODT timing for powerdown mode T0 T1 T2 T3 T4 T5tAONDCKCKCKEODTIntern

16DDR2 Device Operations & Timing DiagramODT timing mode switch at entering power down modeT-5 T-4 T-3 T-2 T-1 T0CKCKT1CKEODTInternalTerm Res.tISt

17DDR2 Device Operations & Timing DiagramODT timing mode switch at exiting power down modeT0 T1 T4 T5 T6 T7CKCKT8CKEODTInternalTerm Res.tIStAOFPDm

18DDR2 Device Operations & Timing Diagram1.3 Bank Activate CommandThe Bank Activate command is issued by holding CAS and WE HIGH with CS and RAS L

19DDR2 Device Operations & Timing Diagram1.4 Read and Write Access ModesAfter a bank has been activated, a read or write cycle can be executed. Th

2DDR2 Device Operations & Timing DiagramContents1. Functional Description1.1 Simplified State Diagram1.2 Basic Function & Operation of DDR2 SD

20DDR2 Device Operations & Timing Diagram1.4.1 Posted CAS Posted CAS operation is supported to make command and data bus efficient for sustainable

21DDR2 Device Operations & Timing Diagram1.4.2 Burst Mode OperationBurst mode operation is used to provide a constant flow of data to memory locat

22DDR2 Device Operations & Timing Diagram1.4.3 Burst Read Command The Burst Read command is initiated by having CS and CAS LOW while holding RAS a

23DDR2 Device Operations & Timing DiagramThe minimum time from the burst read command to the burst write command is defined by a read-to-write-tur

24DDR2 Device Operations & Timing DiagramThe seamless burst read operation is supported by enabling a read command at every other clock for BL = 4

25DDR2 Device Operations & Timing DiagramReads interrupted by a readBurst read can only be interrupted by another read with 4 bit burst boundary.

26DDR2 Device Operations & Timing Diagram1.4.4 Burst Write Operation The Burst Write command is initiated by having CS, CAS and WE LOW while holdi

27DDR2 Device Operations & Timing Diagram The minimum number of clock from the burst write command to the burst read command is [CL - 1 + BL/2 +t

28DDR2 Device Operations & Timing Diagram The seamless burst write operation is supported by enabling a write command every other clock for B

29DDR2 Device Operations & Timing DiagramWrites interrupted by a writeBurst write can only be interrupted by another write with 4 bit burst bounda

3DDR2 Device Operations & Timing DiagramSelfIdleSettingEMRBankPrechargingPowerWritingACTRDAReadSRFREFCKEL(E)MRCKEHCKEH CKELWriteAutomatic Sequence

30DDR2 Device Operations & Timing Diagram1.4.5 Write data maskOne write data mask (DM) pin for each 8 data bits (DQ) will be supported on DDR2 SDR

31DDR2 Device Operations & Timing Diagram1.5 Precharge OperationThe Precharge Command is used to precharge or close a bank that has been activated

32DDR2 Device Operations & Timing Diagram CMDNOP NOP PrechargeNOPDQ’sNOPCK/CKDOUT A0DOUT A1DOUT A2DOUT A3READ APost CASRL =4 DQS/DQSActiveBank A&

33DDR2 Device Operations & Timing DiagramCMDNOP NOP NOP NOPDQ’sPrecharge ACK/CKDOUT A0DOUT A1DOUT A2DOUT A3READ APosted CASAL = 2CL =3RL =5 DQS/DQ

34DDR2 Device Operations & Timing DiagramCMDNOP NOP NOP NOPDQ’sPrecharge ACK/CKDOUT A0DOUT A1DOUT A2DOUT A3READ APost CASAL = 0CL =4RL = 4DQS/DQSA

35DDR2 Device Operations & Timing DiagramBurst Write followed by PrechargeMinimum Write to Precharge Command spacing to the same bank = WL + BL/2

36DDR2 Device Operations & Timing Diagram1.6 Auto Precharge OperationBefore a new row in an active bank can be opened, the active bank must be pre

37DDR2 Device Operations & Timing Diagram CMDNOP NOP NOPNOPDQ’sNOPCK/CKDOUT A0DOUT A1DOUT A2DOUT A3READ APost CASRL =4 DQS/DQST0 T2T1 T3 T4 T5 T6

38DDR2 Device Operations & Timing DiagramCMDNOP NOP NOP NOP NOPDQ’sNOPCK/CKT0 T2T1 T3 T4 T5 T6 T7 T8DOUT A0DOUT A1DOUT A2DOUT A3READ APost CASAL =

39DDR2 Device Operations & Timing DiagramBurst Write with Auto-Precharge If A10 is HIGH when a Write Command is issued, the Write with Auto-Prech

4DDR2 Device Operations & Timing Diagram1.2 Basic Function & Operation of DDR2 SDRAMRead and write accesses to the DDR2 SDRAM are burst orient

40DDR2 Device Operations & Timing DiagramPrecharge & Auto Precharge ClarificationNote 1: RTP[cycles] = RU{tRTP(ns)/tCK(ns)}, where RU stands f

41DDR2 Device Operations & Timing DiagramTo allow for improved efficiency in scheduling and switching between tasks, some flexibility in the absol

42DDR2 Device Operations & Timing Diagram- Device must be in the “All banks idle” state prior to entering Self Refresh mode.- ODT must be turned o

43DDR2 Device Operations & Timing Diagram1.8 Power-DownPower-down is synchronously entered when CKE is registered LOW (along with Nop or Deselect

44DDR2 Device Operations & Timing DiagramCKCMDCKEDQDQSCMDCKEDQDQSCKAL + CLCKE should be kept HIGH until the end of burst operation.AL + CLQ Q Q QQ

45DDR2 Device Operations & Timing DiagramCMDCKEDQDQSCMDCKEDQDQST0 Tm+1 Tm+3 Tx Tx+1 Tx+2 TyT1 Tm Tm+2 Ty+1 Ty+2 Ty+3WRWRBL=8D D D DD D D D D D D D

46DDR2 Device Operations & Timing DiagramCMDCKECMDCKET0 T3 T5 T6 T7 T8 T9T1 T2 T4 T10CMDCKECMDCKECKE can go to LOW one clock after an Active comma

47DDR2 Device Operations & Timing Diagram1.9 Asynchronous CKE LOW EventDRAM requires CKE to be maintained “HIGH” for all valid operations as defin

48DDR2 Device Operations & Timing DiagramInput Clock Frequency Change during Precharge Power DownDDR2 SDRAM input clock frequency can be changed u

49DDR2 Device Operations & Timing Diagram1.10 No Operation CommandThe No Operation command should be used in cases when the DDR2 SDRAM is in an id

5DDR2 Device Operations & Timing DiagramIf OCD calibration is not used, EMR OCD Default command (A9=A8= A7=1) followed by EMR OCD Calibra-tion Mod

50DDR2 Device Operations & Timing Diagram2. Truth Tables2.1 Command truth table.Function CKECS RAS CAS WEBA0BA1BA2A15-A11 A10 A9 - A0 NotesPrevio

51DDR2 Device Operations & Timing Diagram2.2 Clock Enable (CKE) Truth Table for Synchronous 2.3 Data Mask Truth TableCurrent State 2CKECommand (N)

52DDR2 Device Operations & Timing Diagram 3.1 Absolute Maximum DC Ratings3.2 Operating Temperature ConditionSymbol Parameter Rating Units Notes V

53DDR2 Device Operations & Timing Diagram4.1 DC Operation Conditions 4.1.1 Recommended DC Operating Conditions (SSTL_1.8) 4.1.2 ODT DC electrical

54DDR2 Device Operations & Timing Diagram4.2.1 Input DC Logic Level 4.2.2 Input AC Logic Level Notes:1. Refer to Overshoot/undershoot specificatio

55DDR2 Device Operations & Timing Diagram4.2.4 Differential Input AC logic Level 1. VIN(DC) specifies the allowable DC execution of each input of

56DDR2 Device Operations & Timing Diagram4.2.6 Overshoot/Undershoot SpecificationParameterSpecificationDDR2-400DDR2-533DDR2-667DDR2-800Maximum pea

57DDR2 Device Operations & Timing DiagramPower and ground clamps are required on the following input only pins:1. BA0-BA22. A0-A153. RAS4. CAS5. W

58DDR2 Device Operations & Timing Diagram4.3 Output Buffer Characteristics4.3.1 Output AC Test Conditions 4.3.2 Output DC Current Drive Symbol Par

59DDR2 Device Operations & Timing Diagram4.3.3 OCD default characteristics Note:1. Absolute Specifications (0°C ≤ TCASE ≤ +tbd°C; VDD = +1.8V ±0.1

6DDR2 Device Operations & Timing Diagram1.2.2.1 DDR2 SDRAM Mode Register (MR)The mode register stores the data for controlling the various operat

60DDR2 Device Operations & Timing Diagram4.4.1 Full Strength Default Pulldown Driver Characteristics Pulldown Current (mA

61DDR2 Device Operations & Timing Diagram4.4.2 Full Strength Default Pullup Driver Characteristics0.20.30.40.50.60.70.80.91.01.11.21.31.41.51.61.7

62DDR2 Device Operations & Timing Diagram4.4.3 Calibrated Output Driver V-I CharacteristicsDDR2 SDRAM output driver characteristics are defined fo

7DDR2 Device Operations & Timing Diagram1.2.2.2 DDR2 SDRAM Extended Mode Register EMR(1)The extended mode register(1) stores the data for enablin

8DDR2 Device Operations & Timing DiagramAddress FieldRDQSExtended Mode RegisterDLL0*1D.I.C BA0A15 ~ A13A11A10A9A8A7A6A5A4A3A2A1A0A0 DLL Enable0 En

9DDR2 Device Operations & Timing DiagramEMR(2)The extended mode register(2) controls refresh related features. The default value of the extended m